Senior Analog/Mixed-Signal IC Design Engineer

About Synopsys

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

About the Role

In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed (>100Gbps) analog integrated circuits in the latest FinFET process nodes. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

Our Interface IP group in Mississauga,ONis looking for an enthusiastic person to join our team. You will be working with a cross functional team of analog and mixed signal circuit designers from a wide variety of backgrounds on design and methodology. This position requires sound technical experience in full custom analog/mixed-signal circuit design, custom layout, circuit simulations, reliability investigation, post-silicon characterisation and a deep understanding of silicon IP design requirements with the ability to drive and train junior engineers to become experts with new methodologies.

What You'll Be Doing

• Review SerDes standards to develop analog top and sub-block specifications.
• Ability to drive projects and guide junior engineers.
• Exercise independent judgement to identify and refine circuit architectures to achieve optimal power, area and performance targets.
• Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
• Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
• Review and present simulation data for peer and customer review.
• Define and document design features and test plans.
• Propose solutions for post-silicon design updates.

The Impact You Will Have

• Your circuit architectures will define the power, performance, and area of SerDes IP used in high-speed networking and data center applications worldwide
• The design strategies and verification methods you establish will become the foundation for how the team approaches future process nodes and speed grades
• Junior engineers you mentor will carry forward the design discipline and technical rigor that separates IP that works from IP that almost works
• Your layout oversight will directly reduce spins by catching reliability and performance issues before they reach silicon
• The test plans and documentation you create will accelerate post-silicon debug and customer adoption timelines
• Your post-silicon problem-solving will inform the next generation of design rules and best practices across the IP portfolio
• The simulation methodologies you refine will improve design quality and reduce verification time for the entire analog team

What You'll Need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of IC design experience, or Master's or PhD with 1+ years of hands‑on design experience
• Design experience in high speed PHY
• In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
• Design experience with one, and familiarity with several other SerDes sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage‑controlled oscillator, phase mixer, delay‑locked loop, phase locked loop, bandgap reference, ADC, DAC.
• Familiarity with custom digital design (i.e. high‑speed critical paths).
• Knowledge of design for reliability (i.e. EM, IR, aging, etc.)
• Expertise of layout effects (i.e. matching, reliability, proximity effects, etc.).
• Experience with tools for schematic entry, physical layout, and design verification.
• Expertise of SPICE simulators and simulation methods.
• Knowledgeable in Verilog‑A for analog behavioural modeling and simulation‑control/data‑capture.
• Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired
• Hands‑on experience with physical layout of high‑speed circuits is a plus
• Good communication and documentation skills

Who You Are

• You can look at a SerDes standard, extract the critical performance requirements, and translate them into block‑level specs that your team can actually design to
• When a junior engineer brings you a circuit that is not converging, you do not just tell them what to fix, you walk them through why it is not working and what to look for next time
• You push back when a power target does not align with the performance requirement, and you can explain the trade‑off clearly enough that the system architect understands the constraint
• You know which simulation corners actually matter for your circuit and which ones are checkbox exercises, and you are not afraid to say so in a design review
• Layout reviews do not scare you. You can sit with a layout engineer, zoom into a critical net, and have a productive conversation about shielding, symmetry, and current density
• You document your work in a way that makes sense to the person who will debug it six months from now, because you have been that person

The Team You'll Be Part Of

You will join the Interface IP group in Mississauga, ON, a cross‑functional team of analog and mixed‑signal designers working on high‑speed SerDes IP in the latest FinFET process nodes. The team operates with a full suite of industry‑standard IC design tools supplemented by custom in‑house automation supported by an experienced CAD and software team. This is a growing R&D organization focused on delivering SerDes IP that exceeds 100Gbps for networking, data centers, and AI applications. You will collaborate closely with digital designers, verification engineers, layout specialists, and product engineering teams across Synopsys.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.