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Digital Design Engineer (W/M)

IC'ALPS

Grenoble · On-site Full-time Mid Level €48k – €57k/yr 1mo ago

About the role

About

As a subsidiary of SEALSQ CORP (NASDAQ: LAES), based in Grenoble and Toulouse, IC’Alps designs analog and digital integrated circuits ("ASIC-Application Specific Integrated Circuit") for medical applications, as well as for the automotive, security, and other markets.

Your missions

  • In a team of a dozen digital designers (with either design or verification skills), the candidate will be involved in the design of System-on-Chip, IP and full custom ASIC (RISC-V multi-cores for multi sensors platform, custom ultra-low power ASIC for pacemaker application).
  • With the support from SoC architect, translate application requirements into detailed technical specifications for some functions/features of the circuit.
  • Perform the RTL design of those digital blocks according to their specification.
  • Perform basic functional verification and first logic synthesis of the modules designed before delivering them to the verification team and the physical implementation team.
  • Contribute to improve the digital design flow.
  • Help resolve technical issues during the design, the physical implementation, and the industrialization of the circuit.

Your profile

  • Master’s Degree or Ph.D. in Microelectronics or equivalent.
  • 5-7 years of working experience in RTL design.
  • Master RTL languages (VHDL and/or Verilog and/or SystemVerilog) and tools such as Lint and CDC.
  • Good knowledge of the complete ASIC design flow.
  • Comfortable in scripting (python, tcl, …).
  • Experience with seeing a project through from beginning to completion with strong customer interaction.
  • Excellent analytical and problem-solving skills.
  • Ability to work independently but with a strong team spirit, while being a real force of proposals.
  • Written and verbal communication skills.
  • Curiosity, interest for final applications, rigor and requirement in the quality of work.
  • Fluent English; nice to have French.
  • Bonuses: knowledge of different tools (Siemens, Synopsys, Cadence), experience in mixed ASIC environment, knowledge of low-level SW routines for processor-based system.

Conditions

  • Type of employment: permanent, full time.
  • Location: Grenoble (Saint Martin d’Hères) - France.
  • Salary: competitive package, depending on the profile.
  • Join a group with impact and growing perspectives.
  • Pleasant working environment and good team spirit.
  • Team of rigorous professionals, ambitious in their objectives, open in their operation.
  • Fast and reactive in its decisions.

Invitation

If you like to join a design team fully dedicated to the success of the project, from the requirements specifications serving customers’ applications, to the measurements on silicon and the production monitoring, if you are curious and motivated to learn new skills and share your own, do not hesitate!

Join a dynamic company to take technical challenges as a team, in designing integrated circuits for diverse application needs.

Skills

ASIC design flowCadenceCDCLintPythonSiemensSynopsysSystemVerilogTclVHDLVerilog

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