Expert IC Layout Engineer

About

Lead silicon chip innovation as an Expert IC Layout Engineer. Utilize your advanced skills in layout design for DDR and HBM PHY IPs using modern process technologies.

As an integral part of the team, you’ll focus on creating high-quality layouts while ensuring compliance through rigorous physical verification processes. Your role requires a thorough understanding of deep submicron effects and collaborative interaction with cross-disciplinary teams to optimize performance, power, and layout efficiency. Delivering quality checks and troubleshooting will enhance the development pipeline.

Help advance silicon technologies by employing your expertise in layout design and verification.

Key Responsibilities

• Create high-quality layouts using modern technologies
• Conduct comprehensive physical verifications
• Perform critical checks including DRC and LVS
• Troubleshoot and resolve layout challenges
• Document methodologies to promote knowledge sharing

Requirements

• BTech/MTech in Electronics or related discipline
• Minimum 2 years of experience in IC layouts
• Proficiency in DRC, LVS, and Antenna checks
• Familiarity with layout tools like Cadence
• Strong analytical and debugging skills