High-Speed Layout Engineering Leader

About

Elevate your career with Synopsys as a High-Speed Layout Engineering Leader, where your expertise in analog mixed-signal design will contribute to groundbreaking technology. Influence the future of SerDes IP development today.

In this pivotal role, you will manage and innovate high-speed layout processes for SerDes technology. Your understanding of multi-Gbps NRZ and PAM4 will empower you to lead cross-functional teams and facilitate effective communication between stakeholders. You'll also provide mentorship and develop best practices to enhance team capabilities.

Key Responsibilities

• Define layout scope, schedules, and customer requirements
• Innovate analog/mixed-signal layout methodologies
• Lead hands-on debugging and problem resolution
• Collaborate on advanced packaging layout approaches
• Maintain technical documentation and workflow guides

Requirements

• Expertise in analog and mixed-signal circuits
• Proficiency in Synopsys Custom Compiler
• Deep understanding of layout debugging techniques
• Experience with project tracking tools like Jira
• Strong mentoring and communication skills

Contribute to developing high-quality SerDes technologies at Synopsys, shaping the next wave of innovation.