Analog Layout Engineer

About

Take the helm as an Analog Layout Engineer, leading the future of semiconductor technologies with advanced DDR/HBM PHY IPs. Your expertise in layout design will drive excellence in high-performance silicon solutions.

In this role, your strong foundation in CMOS and FinFET technologies will come to life with a focus on innovative layout development. You will guide junior engineers and collaborate across teams to enhance product quality and address complex layout challenges. Key areas of expertise include ESD, latch-up, and rigorous layout reviews.

Contribute your technical skills to shape groundbreaking solutions that accelerate the delivery of innovative semiconductor technology while fostering a collaborative team environment.

Responsibilities

• Spearhead design and development of DDR/HBM PHY layouts
• Ensure precision in layout deliveries adhering to industry standards
• Foster team growth through mentoring of junior engineers
• Estimate project timelines and manage collaborative efforts
• Oversee quality assurance and layout reviews

Requirements

• BTech/MTech in Electrical Engineering or similar
• Minimum 5 years in layout design for advanced technologies
• Proficient in ESD, latch-up, and advanced matching techniques
• Proven ability to lead projects on tight deadlines
• Strong communication skills and detail orientation