Lead Engineer
Synopsys
About the role
About
Drive innovation in RTL design as a Lead Engineer at Synopsys. Leverage your expertise in ASIC development and mentorship to enhance design quality and project efficiency.
As a Lead Engineer at Synopsys, you will be at the forefront of ASIC or PHY IP development with over five years of experience. Your role will focus on developing RTL specifications, collaborating with cross-functional teams, and mentoring junior engineers in Ho Chi Minh City, Da Nang, or Hanoi. With a strong foundation in electronics or telecommunications, you will be solving complex technical challenges while supporting the RTL to GDS flow.
Key Responsibilities
- Develop specifications and architectures for High Bandwidth Interface PHY IP
- Define synthesis constraints and resolve simulation issues
- Collaborate for design and debugging with various teams
- Lead projects and train junior engineers
- Engage with customers to address technical RTL challenges
Requirements
- BS/MS/PhD in Electronics Engineering or Telecommunications
- 5+ years of RTL design experience
- Expertise in VCS, Verdi, and scripting languages
- Knowledge of APB and JTAG protocols
- Strong English communication skills
Elevate your career in RTL design and contribute to groundbreaking technology at Synopsys.
Skills
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