Staff Engineer, Neural Network Optimization

About Lattice Semiconductor

Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products.

The Company's broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.

Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what’s next.

Job Description

Experience Range: 12+ years of hands-on experience in developing, optimizing, and deploying production-grade neural network models, with significant expertise in resource-constrained edge/embedded AI systems (FPGAs, NPUs, or similar low-power accelerators)

As a staff-level technical leader, you will define and drive the technical strategy for next-generation neural network models and optimization techniques for ultra-efficient edge inference. Your work will focus primarily on Lattice sensAI FPGA-based solutions, while also delivering optimized models and reference implementations for other edge platforms (such as NXP processors/NPUs and comparable hardware accelerators) to support broader customer ecosystems in industrial, automotive, consumer, and IoT applications.

You will pioneer advanced efficiency breakthroughs (hardware-aware NAS, mixed-precision quantization, structured sparsity), mentor senior engineers, align ML direction with hardware/compiler roadmaps, and evolve the sensAI Model Zoo into an industry benchmark resource that enables cross-platform portability and benchmarking.

Key Responsibilities

• Lead technical strategy and architecture for neural network development, compression, and deployment primarily on Lattice sensAI platforms, extending optimizations and reference models to other edge hardware (e.g., NXP NPUs, Arm-based accelerators) across multiple product lines and customer segments.
• Design and champion advanced reference NN models using Keras, TensorFlow, PyTorch, and ONNX, spanning CNNs, Transformers, hybrids, and emerging edge-efficient designs suitable for Lattice FPGAs and cross-platform inference.
• Pioneer state-of-the-art compression techniques: hardware-aware Neural Architecture Search (NAS), mixed-precision/activation-aware quantization for ultra-low-power edge inference on diverse accelerators.
• Drive major efficiency gains in latency, power, and throughput on Lattice FPGAs while ensuring portability and performance on other platforms for real-world video/image applications.
• Act as primary technical partner to the ML compiler and soft IP teams, identifying deep bottlenecks and defining model/compiler co-optimizations for Lattice and compatible runtimes on other hardware.
• Own the long-term vision and evolution of the Lattice sensAI Model Zoo — strategy, automated benchmarking, reference designs, and industry-standard pre-trained/optimized models with cross-platform support.
• Mentor and coach senior ML engineers on edge-efficient design, hardware-aware optimization (including multi-platform considerations), and full-stack debugging.
• Evaluate emerging research/tools (advanced NAS, edge runtimes like TensorFlow Lite/ONNX Runtime) and drive pragmatic adoption into the sensAI roadmap and extensions to other platforms.
• Lead creation of sophisticated test frameworks, datasets, and evaluation pipelines for compiler/accuracy/real-world edge validation across platforms.

Required Skills and Qualifications

• 7+ years experience in edge AI model development/optimization/deployment
• Expert mastery of TensorFlow, Keras, PyTorch, ONNX, and conversion tools for cross-platform portability
• Deep expertise in efficient architectures and advanced compression (hardware-aware NAS, quantization, sparsity, distillation)
• Hands-on with edge runtimes (TensorFlow Lite, ONNX Runtime) and accelerators (NPUs, custom AI chips)
• Proven full-stack bottleneck resolution (model -> compiler -> hardware) across diverse platforms
• Experience scaling end-to-end edge ML pipelines (benchmarking, regression, continuous optimization) with multi-platform focus
• Outstanding mentorship, communication, and cross-functional leadership skills
• Master’s or PhD in CS, EE, AI/ML or related field strongly preferred