PCB Layout Design Engineer(Principal/Senior Staff)

TITLE

PCB Layout Design Engineer (Principal/Senior Staff Engineer)

LOCATION

Greater Bengaluru Area

Company Description

We are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, we have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.

Job Description

Seeking Senior PCB Layout Design Engineers who will own the physical design of complex, high-speed PCBs from initial stack-up definition through final fabrication release — collaborating with Systems, SI, PI and mechanical engineers to deliver manufacturable boards.

Key Responsibilities

• Lead end-to-end layout for multilayer boards (>10 layers) supporting High speed Serdes Interface (up to 224G) and High power solutions (KW)
• Create and maintain footprints in the library and validate
• Feasibility studies for various system and board configurations and identifying the tradeoffs
• Define HDI stack-up co-optimization balancing between SI and PI requirements
• Perform constraint-driven routing of critical nets — length matching, differential pair tuning, via stub minimization
• Collaborating with package designer in definition and optimization of the ballmap
• Collaborate with Systems, SI, PI, Packaging and Mechanical Engineers
• Drive DFM/DFT reviews with contract manufacturers

Required Qualifications

• 10+ years of professional PCB layout experience on high-speed Serdes designs and high power
• Deep proficiency in Cadence Allegro tool
• Proven hands‑on experience defining the HDI stack-up and designing HDI boards with blind/buried vias
• Demonstrated expertise in symbol and footprint generation from scratch
• Solid understanding of SI design: breakout, via stubs, loss, crosstalk and impedance requirements
• Solid understanding of PDN design: decoupling solution, power stage and inductor design, isolation requirements
• B.S. in Electrical Engineering, Electronics Technology, or equivalent demonstrated experience

Preferred Qualifications

• Worked on PCIe Gen6/7 and 112G/224G Ethernet interfaces
• Familiarity with OCP / Open Rack (ORV3/ORW) form factors for datacenter board designs
• Understanding of the various connector solutions for high speed Serdes
• Hands‑on experience working from the start to the finish of the PCB design

Tools

• Cadence Allegro
• Siemens Xpedition Schematic

Contact

Sumit S. B
Practice Head (Talent Acquisition, Semiconductors Domain)
Email: sumit@mulyatech.com
Website: www.mulyatech.com
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