Principal Engineer

About

Join a leading technology team as a Principal Engineer focusing on ASIC verification. Utilize your deep knowledge of verification methodologies and protocols to influence the next generation of connectivity solutions.

You will design and implement state-of-the-art verification environments for complex serial protocols. Your experience will involve managing regression, developing comprehensive test cases, and coding for functional coverage. Collaborating closely with RTL designers and a global engineering team, you will enhance chip reliability and performance.

Lead advancements in ASIC verification, supporting high-performance silicon chip development for various applications.

Key Responsibilities

• Architect and implement verification environments for IP cores
• Design verification tasks at unit and system levels
• Develop test cases and debug verification metrics
• Manage regression tests and adherence to methodologies
• Collaborate globally with verification engineers

Requirements

• BSEE with 12+ years or MSEE with 10+ years of relevant experience
• Proficient in System Verilog and industry simulators
• Experienced in VMM, OVM, and UVM methodologies
• Familiar with various serial communication protocols
• Expertise in Verilog and scripting languages