Principal Engineer

About

Elevate PCIe PHY IP verification as a Principal Engineer. Lead the strategy and execution, applying advanced methodologies to enhance performance and efficiency in high-speed silicon solutions.

In this pivotal role, you will drive the functional quality of next-generation PCIe PHYs. You will be responsible for developing comprehensive verification plans while collaborating closely with cross-functional teams. Your expertise in digital verification methodologies and mixed-signal designs will be essential in meeting demanding project targets.

Key Responsibilities

• Define verification strategy for PCIe PHY IPs
• Develop verification plans for mixed-signal designs
• Architect advanced testbench environments
• Verify key PCIe PHY features and compliance
• Collaborate with design and validation teams

Requirements

• Extensive experience in ASIC/IP verification
• Expertise in PCIe and mixed-signal environments
• Proficient in SystemVerilog, UVM, and assertions
• Strong debugging and problem-solving abilities
• Proven mentorship and leadership experience

Drive innovation in verification and contribute to groundbreaking high-speed silicon solutions.