Remote RTL Design Engineer

About Mercor

Mercor, based in San Francisco, connects exceptional talent with leading AI labs. We are seeking an experienced RTL Design Engineer for a 3+ month contract, working 40 hours a week. The role focuses on enhancing AI model training, implementing RTL components, and ensuring seamless integration through collaboration.

Key Responsibilities:

• Evaluate and enhance AI model training for chip design
• Implement RTL components using Verilog/SystemVerilog
• Develop and maintain ASIC design flows
• Collaborate with architecture and verification teams
• Utilize EDA tools for simulation and coverage analysis

Requirements:

• 3–10 years of RTL design or verification experience
• Proficiency in Verilog/SystemVerilog and UVM
• Strong understanding of digital design fundamentals
• Experience with ASIC design flows and EDA tools
• Familiarity with LLM-based tools in chip design

Utilize your RTL design expertise to drive innovative chip solutions at Mercor.