RTL Design Engineers

About The Job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.

Role Responsibilities

• Evaluate and enhance AI model training for digital chip design and verification.
• Design and implement RTL components using Verilog/SystemVerilog.
• Develop and maintain ASIC design flows including lint, synthesis, and timing analysis.
• Collaborate with architecture, verification, and implementation teams to ensure seamless integration.
• Utilize EDA tools for simulation, waveform debug, and coverage analysis.
• Work independently and asynchronously to meet project deadlines and improve AI model performance.

Qualifications

Must-Have

• 3–10 years of experience in digital RTL design or design verification.
• Strong proficiency in Verilog/SystemVerilog and UVM.
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
• Experience with ASIC design flows and EDA tools.
• Familiarity with leveraging LLM-based tools for chip design and verification workflows.

Preferred

• Knowledge of AMBA protocols (AXI, AHB, APB).
• Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
• Exposure to formal verification or SV/UVM-based design verification.

Start Date

• Week of 04/23; applications reviewed on a rolling basis.

Application Process (Takes 20–30 mins to complete)

• Upload resume
• AI interview based on your resume
• Submit form

Resources & Support

• For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
• For any help or support, reach out to: support@mercor.com

PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.