Senior Design Verification Engineer

About

Are you looking for the next step in your career in UVM Verification? Would you like to learn from skilled experts in a friendly and growing environment with exciting projects? If the answer is yes, then this may be the perfect opportunity for you!

I have a key requirement for an experienced/senior Verification Engineer - to work for an established company based in the Grenoble area - who focuses on design and verification services for a number of major clients.

Responsibilities

As the senior verification engineer, you will be responsible for:

• R&D projects
• development of verification environments (System Verilog / UVM /…)
• VIP components
• giving training to other engineers

Qualifications

• Proven experience with IP or SoC verification experience
• Confident knowledge with SystemVerilog and UVM methodology
• SoC architecture
• Bus communication protocols knowledge - AMBA / AXI etc.
• OOP (Object Oriented Programming) and scripting skills / hardware & software - perl / shel / python / c
• Fluent English - and preferably French