Senior Digital Verification Engineer

About

Join Ciena as a Senior Digital Verification Engineer and enhance your expertise in functional verification within a flexible, people-first environment. Your role will focus on innovative verification strategies for advanced Forward Error Correction technology.

Ciena is seeking a Senior Digital Verification Engineer to contribute significantly to the development of the Wavelogic modem family. In this role, you will collaborate with Digital Design Engineers and Architects, utilizing C++, System Verilog, and UVM to create comprehensive verification test plans. Your work will help simulate, validate, and ensure the reliability of functional blocks via robust coverage methods.

Foster innovation and technical growth at Ciena while delivering exceptional verification strategies for industry-leading technology.

Responsibilities

• Read FEC architecture requirements and collaborate with designers
• Develop verification and functional coverage test plans
• Validate architectural FEC blocks using simulation and formal methods
• Create testbench environments with System Verilog UVM and C++
• Monitor verification progress and report on risks

Requirements

• 10+ years of verification experience
• Bachelor's in Electrical, Computer, or Software Engineering
• Significant experience with C/C++, System Verilog, UVM
• Proven ability in digital verification strategies
• Strong problem-solving and decision-making skills