Senior Engineer Plans

About

This section is missing from the provided job description.

Qualifications

• ~8+ years of experience in UVM verification and UVM environment development (must have)
• Proficient in test plan definition and testcase development in C/Assembly/System Verilog
• Expertise in verifying design at RTL level and gate-level simulation
• Good understanding of coverage analysis, performance verification and use-case verification.
• Must have worked on AMBA AXI, AHB, APB protocols
• Should have worked on verifying interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
• Experience in functional test vector development and post-silicon bring-up/debug.
• Fluency with scripting languages (e.g., Perl, Python, Shell)
• Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.
• BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent.

Responsibilities

This section is missing from the provided job description.

Location

Hyderabad, Telangana, India

Department

Verification