Senior Functional Verification Engineer - SoC / UVM

About

We are partnered with a pioneering European semiconductor company specializing in high-performance, low-power processor architectures for data-centric applications. The team is looking to hire a Senior SoC Functional Verification Engineer to play a key role in shaping and validating the next generation of intelligent processors.

This is a permanent working opportunity based in Sophia Antipolis or Grenoble, France.

Responsibilities

• Define and execute global verification strategies and comprehensive test plans.
• Architect and develop UVM-based testbenches and verification platforms at the IP level.
• Design and run complex SoC-level system tests to ensure robust integration.
• Analyze functional coverage metrics to achieve closure and identify architectural gaps.
• Develop high-fidelity reference models to enhance validation accuracy.
• Lead and mentor a small team of engineers and contractors to meet project milestones.
• Collaborate across Design and Software teams in a high-impact environment.

Requirements

• 7+ years of experience in Functional Verification within the semiconductor industry.
• Expert proficiency in SystemVerilog, UVM, and C programming.
• Superior knowledge of state-of-the-art verification methodologies and EDA tools.
• Strong command of the Linux environment (shell, Git/SVN).
• Fluent French and Technical English (written and oral).
• Proven ability to lead technical work-packages or small teams.

Keywords

Senior Verification Engineer / SoC / UVM / SystemVerilog / Functional Verification / MPPA / Processor Design / IP Verification / Coverage Closure / Testbench / Linux / C / Grenoble / Sophia Antipolis / Semiconductor