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Senior Hardware Verification Engineer

European Tech Recruit

France · On-site Contract Senior 3w ago

About the role

Position

Senior Staff Hardware Verification Engineer - Sophia Antipolis

About

Are you passionate about verifying complex IP and system-level designs? Join our client as a Senior Staff Hardware Verification Engineer and help ensure the quality of next-generation silicon using advanced SystemVerilog/UVM verification methodologies.

We are looking for an experienced Senior Staff Hardware Verification Engineer to join our team and help verify complex, highly configurable IP and system-level designs using advanced verification methodologies. You will play a key role in defining verification strategies, improving verification environments, and ensuring high-quality silicon delivery in a demanding technical environment.

Responsibilities

  • Define and implement verification strategies using UVM
  • Develop and extend SystemVerilog RTL testbenches
  • Integrate and maintain third-party Verification IP (VIP)
  • Analyze architecture specifications and validate new features
  • Debug complex failures and monitor regressions and coverage metrics
  • Improve verification flows, automation, and methodologies
  • Support internal teams and resolve technical issues

Requirements

  • Experience in digital design/verification
  • Strong expertise in SystemVerilog and UVM
  • Experience with Arm AMBA protocols
  • Experience integrating verification IP (VIP)
  • Programming experience in Python, C++, Java, Scala, or JavaScript
  • Master’s or PhD in Electronics, Computer Engineering, or related field
  • Fluent French and English

Application

If you are interested please do apply or also feel free to send a copy of your CV direct to me at ccanneaux@eu-recruit.com and we can arrange to speak in more details.

Requirements

  • Experience in digital design/verification
  • Strong expertise in SystemVerilog and UVM
  • Experience with Arm AMBA protocols
  • Experience integrating verification IP (VIP)
  • Programming experience in Python, C++, Java, Scala, or JavaScript
  • Fluent French and English

Responsibilities

  • Define and implement verification strategies using UVM
  • Develop and extend SystemVerilog RTL testbenches
  • Integrate and maintain third-party Verification IP (VIP)
  • Analyze architecture specifications and validate new features
  • Debug complex failures and monitor regressions and coverage metrics
  • Improve verification flows, automation, and methodologies
  • Support internal teams and resolve technical issues

Skills

AMBAC++JavaJavaScriptPythonScalaSystemVerilogUVM

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