Senior IC Layout Engineer

About Us

We are partnering with an innovative Zürich-based tech company who are seeking a motivated Senior IC Layout Engineer, who enjoys full-custom transistor-level design and wants to help shape advanced silicon across modern process nodes. This is a full-time permanently employed position.

If you love precision layout work, deep collaboration with design teams, and pushing PPA, yield, and reliability to the limit — this will be interesting.

What you’ll be doing

This is a hands-on layout role with ownership from concept to tapeout.

Your daily work may include:

• Creating full-custom layouts at both transistor and block level
• Working on mixed-signal, custom-digital, and memory-adjacent layouts
• Planning floorplans and delivering DRC/LVS/PEX-clean designs on advanced nodes
• Applying precision analog layout techniques (matching, symmetry, shielding, guarding, etc.)
• Bridging analog craft with modern FinFET/FDSOI rules and multi-patterning/EUV constraints
• Collaborating closely with analog/custom designers, digital backend teams & verification engineers
• Generating LEF abstracts, constraints, pinouts & integration collateral for macro delivery
• Automating repetitive layout tasks using Python/Tcl (if you enjoy scripting)
• Maintaining guidelines, documentation & contributing to layout best practices

You will work on silicon that goes directly into cutting-edge compute architectures — impact is immediate and visible.

What you’ll bring

You don’t need experience with everything below, but the more you recognize, the better:

• 5+ years in custom IC layout covering analog, memory, or custom-digital blocks
• Experience delivering clean layouts on advanced nodes (sub-28nm, FinFET/FDSOI)
• Strong understanding of analog layout fundamentals: Common-centroid structures, Interdigitation, Current-mirror symmetry, Matching & shielding, Guard rings & substrate isolation
• Ability to work confidently with design & backend teams on extraction, timing, IR & EM topics
• Familiarity with modern layout verification flows (DRC, LVS, PEX)
• Good communication, structured documentation habits & a collaborative mindset

Bonus experience (nice to have but not required)

• Experience with SRAM periphery, redundancy or memory-adjacent layouts
• Knowledge of scan/MBIST routing or macro-level integration
• Exposure to DFM/DFY, ESD/latch-up, or EM/IR reliability checks
• Scripting experience in Tcl or Python for automation
• Prior involvement in macro delivery (LEF, floorplanning, top-level interactions)