Senior Engineer

About

Shape the future of silicon IP as a Senior Engineer. Leverage expertise in IC layout design for next-gen DDR and HBM PHY IPs using advanced technologies and tools. In this role, you will contribute to developing high-quality layouts for cutting-edge memory interface IPs. Your work will involve layout floorplanning, physical verification, and addressing deep submicron effects tailored for 7nm process nodes. You will collaborate within diverse teams, showing creativity and technical prowess across projects while ensuring quality and innovation.

Key Responsibilities:

• Develop layouts for DDR and HBM PHY IPs
• Design floorplans and route layouts accurately
• Conduct physical verifications to meet standards
• Perform DRC, LVS, ERC, and Antenna checks
• Collaborate with teams to optimize layout metrics

Requirements:

• BTech/MTech in Electronics or relevant field
• 2+ years in IC layout for advanced nodes
• Expertise in verification methodologies and tools
• Strong knowledge of deep submicron effects
• Ability to manage tasks independently and collaboratively

Use your skills to drive innovative IP solutions, enhancing semiconductor technology for the future.