Senior Engineer

About

Lead advanced verification in mixed-signal design as a Senior Engineer. Utilize your expertise in AMS co-simulation and digital-analog debugging to enhance high-speed SERDES IP performance.

In this pivotal role, you will define and implement verification test plans to ensure robust quality for SERDES IP. Collaborate with global teams to conduct thorough functional verification and enhance co-simulation environments. Your analytical mindset will drive problem-solving efforts while ensuring silicon reliability through rigorous design checks.

Elevate your career by driving innovation and excellence in mixed-signal verification and reliability.

Responsibilities

• Define and implement comprehensive verification test strategies
• Build and maintain UVM-based System Verilog testbenches
• Perform functional verification on SERDES data paths
• Debug mixed-signal issues and resolve simulation failures
• Conduct design reliability checks like EM and IR analyses

Requirements

• Bachelor's/Master's in Electrical Engineering preferred
• Strong understanding of analog circuits and verification tools
• Proficiency with System Verilog and AMS tools
• Experience in debugging analog-digital interactions
• Excellent communication and collaborative skills