Senior Staff Engineer
Infineon Technologies
About the role
Job Summary
Functional safety Design Verification tools methodology with FMEDA, Generating Fault list & Fault Simulations, coverage analysis w.r.t to ISO26262 standard and ASIL levels
Key Responsibilities
- Experience with FuSa - Functional safety Design Verification tools methodology with FMEDA, Generating Fault list & Fault Simulations, coverage analysis with respect to ISO26262 standard and ASIL levels.
- Working experience with Analog-on-top designs, Mixed signal DV experience in POL (Point of Load), Power stage, Gate drivers or Multi Phase controllers' chips.
- Experience with AI- driven automation for verification workflow, debug acceleration, and automated test plan creation using JAMA.
- Should have developed multiple verification environments for complex IPs and SoCs by defining new test bench architecture, test plan, and using state-of-the-art methodologies such as metric-driven.
- Having knowledge in SoC verification covering RTL, Power Aware and gate-level simulations is preferable.
- Exposure to deployment of automation methods and assertion-based formal verification methodologists preferable.
Qualifications and Skills
- Education: B.E./B.Tech/M.E./M.Tech in Electronics.
- Experience: MS with 8+ years / BS with 9+ years.
- Candidate should have strong background in digital verification to develop advanced testbenches using System Verilog and UVM.
- Collaborate with Design, Analog, AMS team for thorough verification coverage & closure.
Contact
About Infineon
#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in?
We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.
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Click here for more information about Diversity & Inclusion at Infineon.
Requirements
- Candidate should have strong background in digital verification to develop advanced testbenches using System Verilog and UVM.
- Collaborate with Design, Analog, AMS team for thorough verification coverage & closure.
Responsibilities
- Experience with FuSa - Functional safety Design Verification tools methodology with FMEDA, Generating Fault list & Fault Simulations, coverage analysis with respect to ISO26262 standard and ASIL levels.
- Working experience with Analog-on-top designs, Mixed signal DV experience in POL (Point of Load), Power stage, Gate drivers or Multi Phase controllers' chips.
- Experience with AI- driven automation for verification workflow, debug acceleration, and automated test plan creation using JAMA.
- Should have developed multiple verification environments for complex IPs and SoCs by defining new test bench architecture, test plan, and using state-of-the-art methodologies such as metric-driven.
- Having knowledge in SoC verification covering RTL, Power Aware and gate-level simulations is preferable.
- Exposure to deployment of automation methods and assertion-based formal verification methodologists preferable.
Skills
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