Skip to content
mimi

SI​/PI DIC Sr Principle Solutions Engineer

Cadence Design Systems

Remote · US Full-time Lead $144k – $267k/yr 1w ago

About the role

Position

SI/PI for 3DIC Sr Principle Solutions Engineer

About

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Summary

This position involves defining and leading the development of advanced packaging and 3 DIC analysis flows for foundry and customer solutions.

Location

Remote role but must be located in the US.

Responsibilities

  • The candidate will have expert knowledge of the Cadence toolset and/or equivalent competitor toolsets in the context of multiple flows including high‑speed signal design, power design, signal integrity, power integrity and definition of electrical constraints.
  • Design experience and industry knowledge of one of Signal, Power, and Thermal analysis associated with IC, package, or PCB design is required.
  • Ability to analyze the customer's environment and evaluate appropriate solutions.
  • Be knowledgeable and aware of competitive technologies.
  • Anticipates technical issues and develops creative solutions before they become a problem.
  • Takes technical lead on a wide range of projects.
  • Ability to understand high‑speed, high‑performance signal and power integrity‑related issues, and work with peers and other business groups.
  • Able to communicate effectively with Cadence R&D, Product Engineering, Marketing and with customers.
  • Understands customer success criteria and is committed to ensuring customer success.

Requirements

  • Bachelor’s degree (Masters preferred) in Electrical or Electronics Engineering
  • Minimum 15 years experience with Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF related to Package and PCB Design is required
  • 5+ years experience with Cadence SI/PI tools Allegro platform tools including: Sigrity, Clarity, PCB Editor, ICP preferred
  • Strong knowledge of advanced packaging concepts
  • Strong knowledge of 2.5D, 3 DIC and stacked die technologies
  • Understanding of chip level CMOS design concepts desired
  • Strong customer‑facing communication and problem‑solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Excellent verbal and written communication skills

Compensation

The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Benefits

Our benefits programs include:

  • Paid vacation and paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • A variety of medical, dental and vision plan options
  • And more

Closing

We’re doing work that matters. Help us solve what others can’t.

#J-18808-Ljbffr

Requirements

  • Expert knowledge of the Cadence toolset and/or equivalent competitor toolsets in the context of multiple flows including high-speed signal design, power design, signal integrity, power integrity and definition of electrical constraints.
  • Design experience and industry knowledge of one of Signal, Power, and Thermal analysis associated with IC, package, or PCB design is required.
  • Ability to analyze the customer's environment and evaluate appropriate solutions.
  • Knowledgeable and aware of competitive technologies.
  • Anticipates technical issues and develops creative solutions before they become a problem.
  • Takes technical lead on a wide range of projects.
  • Ability to understand high-speed, high-performance signal and power integrity-related issues, and work with peers and other business groups.
  • Able to communicate effectively with Cadence R&D, Product Engineering, Marketing and with customers.
  • Understands customer success criteria and is committed to ensuring customer success.
  • Minimum 15 years experience with Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF related to Package and PCB Design is required.
  • 5+ years experience with Cadence SI/PI tools Allegro platform tools including: Sigrity, Clarity, PCB Editor, ICP preferred.
  • Strong knowledge of advanced packaging concepts.
  • Strong knowledge of 2.5D, 3DIC and stacked die technologies.
  • Understanding of chip level CMOS design concepts desired.
  • Strong customer-facing communication and problem-solving skills.
  • Strong personal drive for continuous learning and expanding professional skill sets.
  • Excellent verbal and written communication skills.

Responsibilities

  • Defining and leading the development of advanced packaging and 3DIC analysis flows for foundry and customer solutions.

Benefits

paid vacationpaid holidays401(k) plan with employer matchemployee stock purchase planmedical plan optionsdental plan optionsvision plan options

Skills

AllegroClarityCMOSCadenceElectromagneticsICPICPCBPCB EditorRFSigritySignal IntegrityThermalPower Integrity

Don't send a generic resume

Paste this job description into Mimi and get a resume tailored to exactly what the hiring team is looking for.

Get started free