Sr Staff/ Staff Engineer: Physical Design

• Participate in the development of Physical Design (PD) methodologies across the RTL-to-GDSII flow using industry-standard tools (Cadence, Synopsys, Mentor). • Perform lead level hands-on work in one or more areas including Synthesis, Formal Equivalence, Place & Route (PnR), Static Timing Analysis (STA), DRC/LVS/IR/EM Signoff at both module and top level. • Take full ownership of the physical design process at the module level and provide support in top-level integration, collaborating closely with RTL designers, DFT teams, and fabrication partners. • Provide technical mentorship, guiding team members and managing PD team interactions to ensure successful SoC implementation. • Drive PPA optimization, including low-power clock tree design for high-performance systems, and achieve timing closure across multiple corners and use cases. • Champion an automation-first approach, developing methodologies in TCL, PERL, or Python to significantly improve team efficiency.

• B.Tech/M.Tech/PhD in Electrical Engineering (EE) or Electronics & Communication Engineering (ECE). • 10+ years of experience in the Physical Design domain. • Deep expertise in one or more areas (Synthesis, Formal Equivalence, PnR, STA, DRC/LVS/IR/EM signoff) with strong working knowledge of the entire PD flow. • Proven track record of successful tapeouts for multi-million gate, multi-hierarchy designs at advanced nanometer technology nodes. • Solid understanding and preferably hands-on experience in low-power design and implementation strategies. • Strong background in automation of PD methodologies using TCL, PERL, or Python. • Willingness to expand beyond core expertise, with a team-oriented, can-do attitude and commitment to mastering the full RTL-to-GDSII flow.