Staff Hardware Design Engineer / Ingénieur Staff Hardware Design F/H
Arteris
About the role
À propos d'Arteris
Arteris permet aux équipes d'ingénierie et de conception des entreprises les plus innovantes au monde de connecter et d'intégrer les systèmes sur puce (SoC) nécessaires aux transformations à venir.
Si vous avez tenu un smartphone, conduit une voiture électronique ou allumé une télévision intelligente, vous avez été en contact avec ce que nous faisons chez Arteris. Ici, l'avenir est littéralement entre vos mains – et quand ce n'est pas le cas, il y a de fortes chances qu'il soit dans un drone qui vous survole, un satellite ou dans le "cloud" d'un centre de données !
Arteris est l'un des principaux fournisseurs d'IP système pour l'accélération du développement de systèmes sur puce (SoC) dans les systèmes électroniques d'aujourd'hui. La propriété intellectuelle d'interconnexion de réseaux sur puce (NoC) et la technologie d'automatisation de l'intégration des systèmes sur puce d'Arteris permettent d'accroître les performances des produits tout en réduisant la consommation d'énergie et en accélérant la mise sur le marché, ce qui se traduit par une amélioration de l'économie des systèmes sur puce et permet aux clients de se concentrer sur l'élaboration des prochaines innovations.
Avec plus de 250 employés, un siège dans la Silicon Valley et des bureaux dans le monde entier, nous sommes un catalyseur de l'innovation SoC pour que les entreprises, des startups aux plus grands leaders du marché technologique, puissent créer efficacement de nouveaux produits avec une flexibilité et une facilité de connectivité éprouvées. Pour en savoir plus, consultez le site www.arteris.com.
About Arteris
Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system‑on‑chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
Arteris is a leading provider of system IP for the acceleration of system‑on‑chip (SoC) development across today’s electronic systems. Arteris network‑on‑chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.
Role Overview
Position: Staff Hardware Design Engineer (Ingénieur Staff Hardware Design)
Your role will be to develop hardware components, ensure delivery on time and with the required quality, and be responsible for the design of an entire system.
Key Responsibilities
- Write architecture specifications for highly configurable on‑chip networks, respecting the most stringent coverage requirements in design verification.
- Contribute to the design of hardware blocks and ensure their quality.
- Participate in the verification methodology and regression environment.
- Communicate with hardware and software teams to ensure product cohesion.
- Maintain and improve existing versions in collaboration with the application engineering team.
- Support colleagues on technical issues.
Experience & Qualifications
- At least 10 years of experience in SoC/IP/NoC designs.
- Experience in coherent and non‑coherent communication protocols and control models (e.g., AMBA, PCIe, CXL, OCP, others) as well as CPU architectures (ARM/RISC‑V).
- Strong experience in SoC/IP design flow (specification, architecture, RTL coding, verification, DFT, synthesis, power and timing closure).
- Excellent problem‑solving, strong communication, and teamwork skills.
- Knowledge of SystemC, Verilog/VHDL/SystemVerilog, Cadence/Synopsys/Mentor Graphics (backend tools), C++, Python, and scripting languages.
- Master’s degree or Doctorate in engineering, computer science, or related fields.
- Fluent in English and French.
Salary
Base salary depending on qualification and experience: 54 KE to 64 KE per year (French version) / 54 KE to 65 KE per year (English version).
Requirements
- Experience in coherent and non-coherent communication protocols and control models (e.g. AMBA, PCIe, CXL, OCP, others) as well as CPU architectures (ARM/RISC V).
- Strong experience in SoC/IP design flow (e.g. specification, architecture, RTL coding, verification, DFT, synthesis, power and timing closure).
- Excellent problem solving, strong communication and teamwork skills.
- Knowledge of SystemC, Verilog/VHDL/System Verilog, Cadence/Synopsys/Mentor Graphic (backend tools), C++, Python, scripting languages.
- Fluent English
Responsibilities
- Write architecture specifications for highly configurable on-chip networks, respecting the most stringent coverage requirements in design verification.
- Contribute to the design of hardware blocks and ensure their quality.
- Participate in the verification methodology and regression environment.
- Communicate with hardware and software teams to ensure product cohesion.
- Maintain and improve existing versions in collaboration with the application engineering team.
- Support colleagues on technical issues.
Skills
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