Vice President of Engineering

Position Summary

TDK AIsight is building the foundational technology stack for next-generation AI wearables, including smart glasses and context-aware devices that combine custom silicon, ultra-low-power sensing, embedded intelligence, multimodal feedback, and cloud-connected software systems. The Vice President of Engineering will lead the end-to-end engineering organization responsible for delivering production-grade hardware, firmware, software, machine learning, and systems platforms that power AI glasses and future wearable products. TDK AIsight publicly describes its platform as enabling context-aware vision, memory, low-power on-device intelligence, eye-intent technology, custom chips, cameras, AI algorithms, and integrated multimodal outputs across visual, audio, haptic, and display subsystems. (AiSight)

This executive must be both a world-class technical leader and a high-output operator who can scale and manage a multidisciplinary organization of ~100 engineers across ASIC/SoC, electrical, mechanical, optics, firmware, Android, RTOS, cloud, data infrastructure, machine learning, computer vision, audio AI, systems integration, validation, and manufacturing engineering. The ideal candidate has deep expertise in wearable systems, silicon-to-cloud product development, and building teams that ship complex products on aggressive schedules.

Key Responsibilities

Executive Engineering Leadership

• Strong ownership and execution at both individual and organizational levels
• High technical judgment with strategic, detailed, and scalable execution
• Data-driven decision making with ability to simplify complexity
• Builds a culture of high standards, accountability, and maintains composure with empathy
• Attracts, develops, and leads top talent to deliver high-impact products

Product & Platform Delivery

• Drive end-to-end execution from concept through EVT, DVT, PVT, manufacturing ramp, launch, and sustaining engineering.
• Deliver integrated platforms for AI glasses and adjacent wearable devices including AR glasses, smart watches, earbuds, and mobile companion devices.
• Translate product requirements into executable engineering plans with measurable milestones, staffing models, dependency tracking, and risk mitigation.
• Own schedule management, critical path resolution, escalation handling, and cross-functional execution with Product, Operations, Quality, Supply Chain, and Business teams.
• Ensure predictable delivery of high-quality products under aggressive timelines.

Hardware Engineering Leadership

• Lead the architecture and development of wearable electronics platforms, overseeing core technologies including embedded systems, sensors, wireless connectivity, power systems, audio/camera, and display interfaces.
• Drive board bring-up, validation, EMC/EMI readiness, reliability, thermal performance, and regulatory readiness.
• Deeply review power budgets, current profiles, battery life models, and real-world power measurements.
• Optimize size, weight, thermal envelope, and manufacturability for wearable form factors.
• Partner with ODM/JDM/CM partners for prototype builds and production readiness.

Firmware / Embedded / Software Leadership

• Lead full-stack development with a focus on embedded systems and platform architecture (including firmware, OS, mobile, cloud, APIs, and analytics).
• Own architecture for low-latency sensor ingestion, event pipelines, OTA updates, device fleet management, observability, and reliability.
• Ensure high software quality through CI/CD, automated testing, release management, and secure SDLC practices.
• Build scalable cloud services that complement on-device inference while minimizing latency, bandwidth, and operating cost.

Machine Learning & Applied AI Leadership

• Lead teams building embedded AI systems for always-on wearables, focused on real-time intelligence (including vision, audio, sensor fusion, and personalization).
• Optimize models for edge deployment across constrained memory, compute, thermal, and battery envelopes.
• Drive quantization, pruning, compilation, runtime acceleration, and benchmarking on custom hardware.
• Build MLOps pipelines for dataset curation, training, evaluation, deployment, monitoring, and continuous improvement.
• Establish metrics for precision/recall, latency, power, robustness, privacy, and user experience.

Silicon / Chip / Architecture Leadership

• Provide technical oversight for custom chips and compute platforms including DSP/MCU/accelerator architectures similar to AIsight’s publicly described SED0112 platform integrating MCU, state machine, and hardware CNN engine. (TDK)
• Lead silicon selection, architecture tradeoffs, specification definition, performance modeling, and vendor management.
• Drive HW/SW co-design across memory bandwidth, compute scheduling, sensor interfaces, interrupt models, power states, and accelerator utilization.
• Evaluate next-generation SoCs, NPUs, image processors, wireless chipsets, and custom ASIC opportunities.

Systems Engineering & Optimization

• Own system-level architecture across chips, firmware, OS, applications, ML runtimes, and cloud services.
• Lead cross-stack optimization focused on performance (including latency, power, thermals, and reliability).
• Establish strong systems integration, root-cause analysis, performance characterization, and field-debug processes.
• Build hardware/software validation labs and automated regression environments.

Vendor / Contractor / External Partner Management

• Manage external contractors and development partners across hardware, firmware, software, test, and manufacturing.
• Define statements of work, deliverables, quality metrics, schedules, and acceptance criteria.
• Hold partners accountable for timelines, technical quality, documentation, and issue resolution.
• Build strategic relationships with component vendors, silicon providers, optics partners, and manufacturing ecosystems.

Required Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, Robotics, or related field.
• 15+ years of engineering leadership experience with increasing scope and organizational responsibility.
• 8+ years leading managers-of-managers and multidisciplinary teams at scale.
• Proven leadership of organizations with 50–100+ engineers across multiple domains.
• Demonstrated success shipping complex consumer electronics, wearables, mobile devices, AR/VR systems, or edge AI products at volume.
• Deep technical expertise in end-to-end system design and integration (spanning hardware, software, ML, chip architecture, system optimization, and AI-driven devices).
• Strong program management instincts with a track record of delivering on schedule.
• Experience managing ODMs, CMs, and engineering contractors.
• Excellent executive communication and cross-functional influence skills.

Preferred Qualifications

• Experience with smart glasses, XR, optical wearables, or always-on context-aware devices.
• Expertise in ultra-low-power architectures and battery-constrained AI systems.
• Experience with custom silicon or ASIC development.
• Strong knowledge of camera pipelines, CV sensors, microphones, and multimodal UX systems.
• Familiarity with privacy-preserving on-device AI architectures.
• Experience operating within global engineering organizations and Asian manufacturing ecosystems.
• Prior VP Engineering, SVP Engineering, or CTO-level leadership in high-growth hardware/software companies.

Compensation and Benefits

The annual base salary range for this role is 250,000 to 300,000 USD. Final compensation will depend on experience, qualifications, and scope. Total compensation may include equity, performance bonuses, long term incentives, and a comprehensive benefits package.

Pay Transparency

Actual compensation may vary based on skills, experience, training, certifications, and location. This range applies to California based candidates and is provided in accordance with pay transparency laws.

Equal Opportunity Employer

We are an equal opportunity employer committed to creating an inclusive environment. All qualified applicants will receive consideration without regard to protected characteristics.