ASIC Digital Verification Engineer

About

Join Synopsys as an ASIC Digital Verification Engineer, focusing on next-gen HBM technology. Be part of a skilled team dedicated to pioneering innovations in silicon chip design.

We are seeking a proactive Engineer with 10-plus years of experience in digital verification to enhance product quality. Your role entails developing verification plans, writing test cases with SystemVerilog and UVM, and debugging intricate design challenges. Work collaboratively to improve methodologies and share best practices within our team.

Make a substantial impact at Synopsys by engaging in innovative projects and improving testing processes.

Key Responsibilities

• Execute comprehensive verification plans for complex ASIC designs
• Maintain and write advanced test cases using UVM and SystemVerilog
• Collaborate closely with design and mixed-signal teams on issues
• Automate workflows using Python or Perl for enhancement
• Document verification results and methodologies for process improvement

Requirements

• BSEE or MSEE with 10+ years in digital design/verification
• Strong skills in SystemVerilog/UVM for test case development
• Excellent debugging abilities with complex issues
• Solid understanding of digital circuit design
• Proven team collaboration skills