co-design engineer

About

We are looking for a co-design engineer for future computing architectures in HPC. This position, in a fixed-term contract, is based at the Nano-Innov site of Paris-Saclay, Essonne (91).

As part of a multidisciplinary team specializing in hardware IP design and EDA tools, you will develop innovative methodologies and tools for HW/SW co-design of electronic architectures, focusing on high-performance computing (HPC) and AI systems.

You will leverage VPSim (virtual prototyping) and A-DECA (architecture exploration)—tools that enable HW modeling, binary SW execution, functional validation, and performance analysis in a fully virtualized environment. These tools integrate QEMU-based emulation, external models, and a Python API for performance data extraction during application execution. A-DECA further supports efficient design space exploration via optimization strategies.

This role is part of EU-funded research projects on next-gen HPC networks and open-source EDA tools, with a focus on optical/photonic interconnects to address latency, bandwidth, and scalability challenges in large-scale computing.

Responsibilities

In the course of your mission, you will be required to :

• Understand the technical specifications of the computing system integrating an optical link and develop appropriate model in VPSim plateform
• Develop a high-level virtual prototype based on CEA VPSIM simulation tool to provide first estimations of KPIs and to allow system-of-chiplets architecture exploration
• Determine best architectural parameters in terms of power, performance, area as well as sustainability using A-DECA tool
• Collaborate/communicate with other research partners involved to expand CEA VPSIM tool to model optical-switch based architectures
• Ability to assess, prepare, and contribute software components to open-source ecosystems
• Participate in the scientific dissemination of the team's research results (contributions to publications in national and international conferences), design of videos, demonstrations and tutorials as well as in the valorization of our innovations.

#CEA-List ; #researcher ; #Nanotechnology ; #Simulation Model

Qualifications

Profil du candidat

You have an engineering/master's degree or a PhD in the field of computer science, electronics or embedded systems.

Required skills/knowledge:

• HW description languages: SystemC, VHDL, Verilog, SystemVerilog, CHISEL
• Knowledge of digital electronic architecture (processors, Caches, NoC, ...)
• High level programming language: C++/Java/Scala ...
• Scripting languages : Bash/Python ...
• Development tools : IDE, make/cmake, svn/git, continuous integration, docker ...
• Git environement

Desired experience and/or skills:

• Experience in simulation/emulation, especially with QEMU
• Knowledge in Linux kernel development
• Experience in other scripting languages (bash, tcl) would be a plus.
• Knowledge in the field of operational research and/or machine learning algorithms would be a plus.

Diversity and Inclusion

In accordance with the commitments made by the CEA to promote the integration of disabled people, this job is open to all. The CEA proposes arrangements and/or organizational possibilities for the inclusion of disabled workers.

Location

Localisation du poste Site

Saclay

Localisation du poste

France, Ile-de-France, Essonne (91)

Ville

Saclay

Candidate Criteria

Langues

• Anglais (Courant)
• Français (Courant)

Application Details

Demandeur Disponibilité du poste

08/06/2026