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Principal Engineer - System on Chip Physical Design

Globalfoundries Engineering Private Limited

Bengaluru · On-site Full-time Lead Yesterday

About the role

Principal Engineer, PD

Title

Principal Engineer, SOC PD

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction

The Principal Engineer, SoC PD leads and mentors engineers towards designing and delivering full chip Physical design. This role drives the creation of custom integrated circuits (ICs) from specifications, derive execution level detail and oversee building a solid re-use methodology, enabling fast turnaround through physical design flows and ensuring project efficiency, quality, and innovation.

Your Job

  • As a leader in Physical Design, you will own and drive all phases of the backend implementation flow for complex SoCs. This includes chip‑level partitioning, synthesis, floorplanning, placement, clock‑tree synthesis, place‑and‑route, timing closure, power and noise analysis, IR/EM reliability, and full physical verification.
  • You will mentor and manage a high‑performing team of RTL‑to‑GDSII physical design engineers, setting technical direction, enabling growth, and ensuring world‑class execution.
  • You will define and deliver ambitious PPA(S) targets through innovation, scalable methodologies, and robust reuse strategies. Collaboration is central to this role—partner closely with cross‑functional teams across DFT, packaging, hardware, program management, IP, and foundry engineering.
  • You will also champion the development, rollout, and adoption of next‑generation EDA tools, flows, and methodologies.

Other Responsibilities

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications

  • Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
  • 12+ years of industry experience, including: 3+ years in technical people management, 7+ years in technical leadership roles
  • Deep hands‑on expertise in end‑to‑end SoC design flows: IP integration, IO ring design, floorplanning, multi‑voltage power planning, data partitioning, MCMM STA, PV, EM/IR, and reliability sign‑off.
  • Strong proficiency with Synopsys, Cadence, or Siemens/Mentor EDA tools.
  • Excellent leadership, project management, and communication skills.
  • Strong analytical mindset with the ability to solve complex timing and power challenges.

Preferred Qualifications

  • Exposure to DFT, AMS integration.
  • Proven track record of delivering custom silicon across diverse application domains.
  • Inspirational leadership style with a passion for mentoring and scaling high‑performance teams.
  • Customer‑centric, proactive problem solver.
  • Passion for continuous learning and driving adoption of industry best practices.

Equal Opportunity Statement

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Benefits

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Experience Level

Senior Level

Requirements

  • Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
  • 12+ years of industry experience, including: 3+ years in technical people management, 7+ years in technical leadership roles
  • Deep hands-on expertise in end-to-end SoC design flows: IP integration, IO ring design, floorplanning, multi-voltage power planning, data partitioning, MCMM STA, PV, EM/IR, and reliability sign-off.
  • Strong proficiency with Synopsys, Cadence, or Siemens/Mentor EDA tools.
  • Excellent leadership, project management, and communication skills.
  • Strong analytical mindset with the ability to solve complex timing and power challenges.

Responsibilities

  • Own and drive all phases of the backend implementation flow for complex SoCs.
  • Mentor and manage a high-performing team of RTL-to-GDSII physical design engineers, setting technical direction, enabling growth, and ensuring world-class execution.
  • Define and deliver ambitious PPA(S) targets through innovation, scalable methodologies, and robust reuse strategies.
  • Champion the development, rollout, and adoption of next-generation EDA tools, flows, and methodologies.
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Skills

CadenceEDAEM/IRIP integrationIO ring designMCMM STAPVSiemensSoCSynopsys

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