Senior Staff Physical Design Engineer
VerticalCompute
About the role
Thank you for sharing the detailed description of the Senior Staff Physical Design Engineer role at Vertical Compute. It sounds like an exciting opportunity to work on cutting‑edge memory technologies and to help shape the future of compute architecture.
While I can’t upload a résumé for you, I’d be happy to help you prepare a strong application package. Here are a few ways I can assist:
| What you might need | How I can help |
|---|---|
| Tailored cover letter | Draft a concise, impact‑focused cover letter that highlights your experience with FinFET physical implementation, multi‑corner timing closure, power‑integrity analysis, and any relevant memory‑IP or in‑memory‑computing projects. |
| Resume / CV polishing | Review your current CV, suggest re‑ordering of sections, add quantifiable achievements (e.g., “Reduced post‑layout IR‑drop by 18 % on a 16 nm SRAM block”), and ensure the language matches the keywords in the job posting. |
| Technical summary | Create a short “Technical Highlights” block that showcases your mastery of tools (Virtuoso, Calibre, Synopsys ICC2/Innovus, PrimeTime), scripting languages (Tcl/Python/Perl), and any experience with emerging memory technologies (MRAM, RRAM). |
| Interview preparation | Provide a list of likely interview topics (e.g., secondary power‑grid design, antenna rule mitigation, DRC/LVS sign‑off flow) and sample answers or talking points to demonstrate depth of knowledge. |
| Portfolio / design snippets | Advise on how to present confidential layout work (e.g., anonymized screenshots, block diagrams, performance metrics) while respecting NDAs. |
| Language & cultural fit | Suggest ways to convey your communication skills, teamwork mindset, and any multilingual abilities (English, French, Dutch) that align with the company’s inclusive culture. |
Quick Draft: Cover‑Letter Opening (you can customize)
[Your Name]
[Your Address] • [City, State, ZIP] • [Phone] • [Email] • [LinkedIn]April 8 2026
Hiring Committee – Vertical Compute
[Company Address]Dear Hiring Committee,
I am excited to submit my application for the Senior Staff Physical Design Engineer position at Vertical Compute. With 12 years of end‑to‑end physical design experience on 28 nm‑to‑14 nm FinFET platforms—including full RTL‑to‑GDSII flows for high‑performance SRAM and emerging MRAM IP—I have consistently delivered PPA‑optimized silicon that meets aggressive timing, power‑integrity, and manufacturability targets. My background aligns closely with the responsibilities outlined in your posting, particularly in secondary power‑grid architecture, multi‑mode multi‑corner timing closure, and advanced DRC/LVS sign‑off using Cadence Virtuoso and Mentor Calibre.
(…continue with specific achievements, leadership examples, and why you’re drawn to Vertical Compute’s mission…)
Feel free to send me your current résumé or any specific sections you’d like to refine, and I’ll provide concrete edits and suggestions. Let’s make sure your application stands out and showcases exactly why you’re the ideal technical pillar for Vertical Compute’s physical design team.
Requirements
- Master’s in Electrical Engineering or related field.
- 10+ years in full-custom layout for memory and/or analog/mixed-signal IPs.
- Deep understanding of physical constraints: matching, EM, IR drop, antenna rules.
- Proficient in layout tools (Virtuoso, Calibre), proficiency in CAD scripting is considered as a big plus.
- Experience with advanced CMOS nodes and emerging memories (MRAM, RRAM) is a plus.
- Experience in in-memory computing layout is a plus.
- Self-motivated, self-directed, and well-organized.
- Excellent communication and interpersonal skills, and ability to engage effectively with your colleagues, our partners, and stakeholders.
- Good English communication skills, knowledge of French and/or Dutch is considered a bonus.
Responsibilities
- Lead the full RTL-to-GDSII physical implementation flow, including synthesis, floorplanning, place & route, CTS, timing closure, and sign-off.
- Define and execute implementation strategies optimized for FinFET technologies, addressing challenges such as secondary power grids, track patterns, and advanced DRC constraints.
- Perform Multi-Mode Multi-Corner (MMMC) timing closure and power optimization to achieve the best PPA (Power, Performance, Area) targets.
- Conduct power integrity analysis and ensure robust IR drop and electromigration (EM) margins.
- Drive physical verification closure including DRC, LVS, ERC, and antenna checks using industry-standard sign-off tools.
- Collaborate closely with RTL and DFT teams to ensure physically aware synthesis, efficient scan-chain integration, and congestion mitigation.
- Interface with foundries and EDA vendors to address technology-specific implementation challenges.
- Contribute to EDA flow improvements and automation through scripting (Tcl, Python, or Perl) to enhance productivity and design quality.
- Act as a technical pillar and mentor within the physical design team, supporting complex debugging and advanced optimization strategies.
Skills
Don't send a generic resume
Paste this job description into Mimi and get a resume tailored to exactly what the hiring team is looking for.
Get started free