Senior engineer- standard cell layout

About

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high‑performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

Responsibilities

• Design and maintain standard cells layout for new DRAM products on new technology.
• Lead the stdcells layout projects from initial spec definition to PPA‑qualified library release.
• Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies.
• Perform layout verification such as LVS, DRC, latchup, quality check, and documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in multiple‑project environments.
• Guide junior team members in their execution of sub‑block‑level layouts and review their work.
• Contribute to effective project management.
• Develop new flows/methodologies to reduce the stdcells manual effort and increase productivity.
• Closely work with the Process team, CMOS, and CAD to negotiate DRC for new technology.
• Co‑work with international colleagues on developing new flows and tools for stdcells layout and design.