RTL Design Engineer, Multimedia and Machine Learning, Silicon

Role Overview: Be part of a diverse team at Google that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. As a member of this team, you will contribute to the innovation of products that are beloved by millions globally. Your expertise will play a crucial role in shaping the future of hardware experiences, ensuring exceptional performance, efficiency, and integration.

Key Responsibilities: - Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. - Conduct RTL verification using industry standard methodologies and actively participate in test planning and coverage analysis. - Develop RTL implementations that align with power, performance, and area goals. - Engage in synthesis, timing/power closure, and FPGA/silicon bring-up processes. - Develop tools/scripts to automate tasks and monitor progress effectively.

Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. - Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques. - Experience with a scripting language such as Perl or Python.

Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture. - Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs such as Display or Video Codecs. - Familiarity with ASIC design methodologies for clock domain checks and reset checks. - Excellent C/C++ programming and software design skills. Role Overview: Be part of a diverse team at Google that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. As a member of this team, you will contribute to the innovation of products that are beloved by millions globally. Your expertise will play a crucial role in shaping the future of hardware experiences, ensuring exceptional performance, efficiency, and integration.

Key Responsibilities: - Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. - Conduct RTL verification using industry standard methodologies and actively participate in test planning and coverage analysis. - Develop RTL implementations that align with power, performance, and area goals. - Engage in synthesis, timing/power closure, and FPGA/silicon bring-up processes. - Develop tools/scripts to automate tasks and monitor progress effectively.

Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. - Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques. - Experience with a scripting language such as Perl or Python.

Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture. - Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs such as Display or Video Codecs. - Familiarity with ASIC design methodologies for clock domain checks and reset checks. - Excellent C/C++ programming and software design skills.