Sr. STA Engineer - 4-8Yrs

Job Title: Sr. STA Engineer - 4-8Yrs

Job Location: Bangalore

Job Overview

We are looking for a highly skilled Static Timing Analysis (STA) Engineer with strong expertise in synthesis and timing closure. The ideal candidate should have hands-on experience in logic synthesis, clock tree synthesis, and timing analysis using industry-standard EDA tools.

Key Responsibilities

• Perform Static Timing Analysis (STA) at block and full-chip level • Work on timing closure across all design stages • Handle Logic Synthesis and Clock Tree Synthesis (CTS) • Analyze and fix setup/hold violations, timing bottlenecks, and path optimizations • Collaborate with design, physical design, and verification teams • Generate and analyze timing reports, constraints, and sign-off checks • Ensure timing convergence with PPA (Power, Performance, Area) targets

Preferred Qualifications

• Experience with advanced technology nodes (e.g., 7nm/5nm is a plus) • Knowledge of low-power design techniques • Familiarity with scripting (Tcl, Python) • Strong debugging and problem-solving skills

Required Skills

• Strong experience in: • Logic Synthesis • Clock Tree Synthesis (CTS) • Static Timing Analysis (STA) • Hands-on expertise with tools: • Cadence Genus • Cadence Innovus • Cadence Tempus • Deep understanding of: • Timing constraints (SDC) • Setup/Hold analysis • Multi-mode multi-corner (MMMC) analysis • Timing sign-off methodologie